1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit and, more particularly, to a phase locked loop circuit using a fractional frequency divider, which can set a frequency at a closer step than that of a reference frequency.
2. Description of the Related Art
A known phase locked loop circuit of this kind is shown in FIG. 5.
In a phase comparator (FPD) 2, as shown in FIG. 5, a reference frequency 1 is compared in phase with a signal, which is obtained by dividing the frequency of the output of a voltage-controlled oscillator 4 by a fractional frequency divider 5, thereby to generate a deviation signal. This deviation signal controls the output frequency of the voltage-controlled oscillator 4 through a filter (FIL).
With reference of FIG. 7 to FIG. 10, here will be described the operating principle of the phase locked loop using the fractional frequency divider.
In FIG. 7, there is constructed a PLL (Phase Locked Loop) circuit, in which the frequency of an output of a voltage-controlled oscillator 27 is divided by a variable frequency divider 21, in which the output of the frequency divider 21 is compared in phase with a reference signal 25 by a phase comparator 24, and in which the output of the phase comparator 24 is connected through an LPF 26 with a frequency control input 34 of the voltage-controlled oscillator 27.
FIG. 8 shows the variable frequency divider 21, a counter 36 for counting an output signal F1 of the frequency divider 21, and a switching controller 35 for switching the frequency division ratio of the variable frequency divider 21 according to the counted value. In the case of an average frequency division number of (N+L/A), for example, the frequency of the input signal is divided with a variable frequency number N of the variable frequency divider 21 so that the signal F1 outputted to a signal line 29 is counted to (A−L) by the counter 36. After this, the variable frequency divider 21 is switched to the frequency division number of (N+1) so that its output F1 is counted to A.
When the counting operation is done to A, moreover, the variable frequency divider 21 is switched to the frequency division N.
As shown in FIG. 9, more specifically, this frequency division N is continuously used by (A−L) times, and the frequency division (N+1) is continuously used by L times, so that the fundamental frequency using the repetition as the period T and its higher harmonics are generated on the signal line 29. phase comparator 24 and the LPF 26 (PLL filter) modulate the voltage-controlled oscillator 21 thereby to generate an unnecessary frequency component in the vicinity of an output frequency FO (as referred to FIG. 10).
In another method for obtaining the frequency division of (N+L/A), moreover, the frequency division value may be switched such that the result of averaging the frequency division value may be (N+L/A).
In the phase locked loop circuit of FIG. 5, either the fractional frequency division circuit, in which the denominator of the fractional frequency division has a value of squared 2, or a PLL circuit using an IC having the fractional frequency divider packaged therein, generates an output frequency, which is integer times as large as the value obtained by dividing the reference frequency by the value of squared 2.
If the reference frequency is set in the phase locked loop circuit of FIG. 5 to not the value of squared 2 but a rounded value such as 5 MHz or 10 MHz, however, a fraction results for a desired output frequency other than a predetermined one.
In the case of FIG. 5, an output frequency Fout is expressed by:Fout=Fref·(M+A/B).In the case of B=2b,Fout=Fref·(M+A/2b).Therefore, the minimum set unit of the Fout is Fref/2b. (In the above, letters other than Fout and Fref are integers of 0 or larger.)
Therefore, in the case of Fref=10 MHz and b=18 in FIG. 5, for example, the output frequency Fout has the minimum set unit of 38 Hz, 146 Hz, - - - , and so on so that it has a fraction but for the case of the specific frequency.
A high-frequency signal generator having an external reference signal input generally has a reference frequency of 10 MHz. In case the high-frequency signal generators are to be synchronized commonly with 10 MHz, as shown in FIG. 6, one high-frequency generator −1 is constructed of a synthesizer of the PLL circuit using the fractional frequency divider of the prior art, as shown in FIG. 5, and the other high-frequency generator −2 is constructed of a synthesizer (of the second PLL stage of FIG. 1) using the ordinary PLL circuit. With these constructions, a frequency deviation is caused to an extent of the fraction irrespective of the common frequency setting, so that no synchronization can be taken.